cpu-features.h 5.8 KB

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  1. /*
  2. * Copyright (C) 2008 The Android Open Source Project
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions
  7. * are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in
  12. * the documentation and/or other materials provided with the
  13. * distribution.
  14. *
  15. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  18. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  19. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  20. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  21. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  22. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  23. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  24. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  25. * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26. * SUCH DAMAGE.
  27. */
  28. #ifndef _ARM_MACHINE_CPU_FEATURES_H
  29. #define _ARM_MACHINE_CPU_FEATURES_H
  30. /* The purpose of this file is to define several macros corresponding
  31. * to CPU features that may or may not be available at build time on
  32. * on the target CPU.
  33. *
  34. * This is done to abstract us from the various ARM Architecture
  35. * quirks and alphabet soup.
  36. *
  37. * IMPORTANT: We have no intention to support anything below an ARMv4T !
  38. */
  39. /* __ARM_ARCH__ is a number corresponding to the ARM revision
  40. * we're going to support
  41. *
  42. * it looks like our toolchain doesn't define __ARM_ARCH__
  43. * so try to guess it.
  44. *
  45. *
  46. *
  47. */
  48. #ifndef __ARM_ARCH__
  49. # if defined __ARM_ARCH_7__ || defined __ARM_ARCH_7A__ || \
  50. defined __ARM_ARCH_7R__ || defined __ARM_ARCH_7M__
  51. # define __ARM_ARCH__ 7
  52. # elif defined __ARM_ARCH_6__ || defined __ARM_ARCH_6J__ || \
  53. defined __ARM_ARCH_6K__ || defined __ARM_ARCH_6Z__ || \
  54. defined __ARM_ARCH_6KZ__ || defined __ARM_ARCH_6T2__
  55. #
  56. # define __ARM_ARCH__ 6
  57. #
  58. # elif defined __ARM_ARCH_5__ || defined __ARM_ARCH_5T__ || \
  59. defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__
  60. #
  61. # define __ARM_ARCH__ 5
  62. #
  63. # elif defined __ARM_ARCH_4T__
  64. #
  65. # define __ARM_ARCH__ 4
  66. #
  67. # elif defined __ARM_ARCH_4__
  68. # error ARMv4 is not supported, please use ARMv4T at a minimum
  69. # else
  70. # error Unknown or unsupported ARM architecture
  71. # endif
  72. #endif
  73. /* experimental feature used to check that our ARMv4 workarounds
  74. * work correctly without a real ARMv4 machine */
  75. #ifdef BIONIC_EXPERIMENTAL_FORCE_ARMV4
  76. # undef __ARM_ARCH__
  77. # define __ARM_ARCH__ 4
  78. #endif
  79. /* define __ARM_HAVE_5TE if we have the ARMv5TE instructions */
  80. #if __ARM_ARCH__ > 5
  81. # define __ARM_HAVE_5TE 1
  82. #elif __ARM_ARCH__ == 5
  83. # if defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__
  84. # define __ARM_HAVE_5TE 1
  85. # endif
  86. #endif
  87. /* instructions introduced in ARMv5 */
  88. #if __ARM_ARCH__ >= 5
  89. # define __ARM_HAVE_BLX 1
  90. # define __ARM_HAVE_CLZ 1
  91. # define __ARM_HAVE_LDC2 1
  92. # define __ARM_HAVE_MCR2 1
  93. # define __ARM_HAVE_MRC2 1
  94. # define __ARM_HAVE_STC2 1
  95. #endif
  96. /* ARMv5TE introduces a few instructions */
  97. #if __ARM_HAVE_5TE
  98. # define __ARM_HAVE_PLD 1
  99. # define __ARM_HAVE_MCRR 1
  100. # define __ARM_HAVE_MRRC 1
  101. #endif
  102. /* define __ARM_HAVE_HALFWORD_MULTIPLY when half-word multiply instructions
  103. * this means variants of: smul, smulw, smla, smlaw, smlal
  104. */
  105. #if __ARM_HAVE_5TE
  106. # define __ARM_HAVE_HALFWORD_MULTIPLY 1
  107. #endif
  108. /* define __ARM_HAVE_PAIR_LOAD_STORE when 64-bit memory loads and stored
  109. * into/from a pair of 32-bit registers is supported throuhg 'ldrd' and 'strd'
  110. */
  111. #if __ARM_HAVE_5TE
  112. # define __ARM_HAVE_PAIR_LOAD_STORE 1
  113. #endif
  114. /* define __ARM_HAVE_SATURATED_ARITHMETIC is you have the saturated integer
  115. * arithmetic instructions: qdd, qdadd, qsub, qdsub
  116. */
  117. #if __ARM_HAVE_5TE
  118. # define __ARM_HAVE_SATURATED_ARITHMETIC 1
  119. #endif
  120. /* define __ARM_HAVE_PC_INTERWORK when a direct assignment to the
  121. * pc register will switch into thumb/ARM mode depending on bit 0
  122. * of the new instruction address. Before ARMv5, this was not the
  123. * case, and you have to write:
  124. *
  125. * mov r0, [<some address>]
  126. * bx r0
  127. *
  128. * instead of:
  129. *
  130. * ldr pc, [<some address>]
  131. *
  132. * note that this affects any instruction that explicitly changes the
  133. * value of the pc register, including ldm { ...,pc } or 'add pc, #offset'
  134. */
  135. #if __ARM_ARCH__ >= 5
  136. # define __ARM_HAVE_PC_INTERWORK
  137. #endif
  138. /* define __ARM_HAVE_LDREX_STREX for ARMv6 and ARMv7 architecture to be
  139. * used in replacement of deprecated swp instruction
  140. */
  141. #if __ARM_ARCH__ >= 6
  142. # define __ARM_HAVE_LDREX_STREX
  143. #endif
  144. /* define __ARM_HAVE_DMB for ARMv7 architecture
  145. */
  146. #if __ARM_ARCH__ >= 7
  147. # define __ARM_HAVE_DMB
  148. #endif
  149. /* define __ARM_HAVE_LDREXD for ARMv7 architecture
  150. * (also present in ARMv6K, but not implemented in ARMv7-M, neither of which
  151. * we care about)
  152. */
  153. #if __ARM_ARCH__ >= 7
  154. # define __ARM_HAVE_LDREXD
  155. #endif
  156. /* define _ARM_HAVE_VFP if we have VFPv3
  157. */
  158. #if __ARM_ARCH__ >= 7 && defined __VFP_FP__
  159. # define __ARM_HAVE_VFP
  160. #endif
  161. /* define _ARM_HAVE_NEON for ARMv7 architecture if we support the
  162. * Neon SIMD instruction set extensions. This also implies
  163. * that VFPv3-D32 is supported.
  164. */
  165. #if __ARM_ARCH__ >= 7 && defined __ARM_NEON__
  166. # define __ARM_HAVE_NEON
  167. #endif
  168. /* Assembly-only macros */
  169. /* define a handy PLD(address) macro since the cache preload
  170. * is an optional opcode
  171. */
  172. #if __ARM_HAVE_PLD
  173. # define PLD(reg,offset) pld [reg, offset]
  174. #else
  175. # define PLD(reg,offset) /* nothing */
  176. #endif
  177. #endif /* _ARM_MACHINE_CPU_FEATURES_H */